1. Field of the Invention
The disclosure relates to an impedance comparison integrated circuit, and more particularly to an impedance comparison integrated circuit for interfacing a sensed signal of a capacitive touch sensor.
2. Description of the Related Art
In general, an impedance comparator detects variation of capacitance induced between a user and an electrode when the user""s approaching the impedance comparator, detects minute variation of resistance induced by variation of an external environment such as variation of humidity, or detects variation of inductance. Also, the impedance comparator may detect variation of complex impedance.
Recently, switches for an LCD monitor have been changed from a conventional push switch type to a touch switch type as.
In the touch switch type switch, electrodes are installed in a front cover of the touch switch product, the switch senses variation of capacitance induced between the electrodes and user when the user touches around the electrodes, and the switch transfers the sensed signal to a microprocessor or a microcomputer etc.
Accordingly, the front cover becomes thicker according as home appliances becomes larger, the capacitance of the touch switch decreases, and the sensed capacitance value has very minute variation, so that there is required a more precise detection of capacitance variation.
In addition, many countries have restricted power consumption of home appliances, especially power consumption in a standby state.
According to the conventional impedance comparison method, a measurement capacitor used for measurement is charged and discharged by current, the frequency or time of the charging and the discharging operation is measured, and the capacitance value is compared by comparing the measured frequency or time with a reference frequency of reference time. In the conventional impedance comparison method, there exist errors of voltage comparator, reference voltage errors of the charging and discharging operation and time delay errors of the switch that controls the charging and discharging operation, so that these errors lead to very large measurement errors of impedance variation.
FIG. 1 is a circuit diagram showing a conventional impedance comparison circuit for touch switch.
Referring to FIG. 1, according to the conventional impedance comparison circuit, a current source and a measurement capacitor to be measured are connected to each other, the charged voltage level charged in the measurement capacitor and the discharged voltage level discharged from the capacitor are compared by means of voltage comparators (U1A, U1B), and capacitance difference is measured by detecting the charging and discharging frequencies or charging time.
For the purpose of comparing the charged voltage in the reference capacitor (CA) with that of the measurement capacitor (CB), an upper reference voltage (VCH) and an lower reference voltage (VCL) is generated at the comparators (U1A, U1B), are applied to a non-inverting terminal (VIN+) of the comparators, and the charging and discharging control switch should be controlled by logic circuits when the charging and discharging operations is finished.
The input offset error Vxe2x80x94offset of the comparators (U1A, U1B) causes an comparison error of the comparators. Also, reference voltage error Vrefxe2x80x94diff is generated in both comparators (U1A, U1B) because different voltages (VCH, VCL) are applied to the comparators (U1A, U1B), so that the sensed output frequency has errors.
Also, a difference of time (Tcs), which is taken to begin the charging operation, between a reference circuit and a measurement circuit is generated because of a basic transmission delay and a difference of transmission path, so that output errors increase.
Accordingly, the final output error (Txe2x80x94outxe2x80x94err) is shown as follows.
Txe2x80x94outxe2x80x94errxe2x88x9d2xc3x97Vxe2x80x94offset+4xc3x97Vrefxe2x80x94diff+2xc3x97Tcsxe2x80x83xe2x80x83Expression 1
According to another conventional impedance comparison circuit that has a voltage comparator (or inverter) and compares the frequency or charging time for the purpose of measuring capacitance variation, there is generated an output error similar to the expression 1. Therefore, in order to use a capacitance comparator with a high precision, another adjustments are required, and manufacturing cost increases. Power consumption of the comparator increases because current source for charging operation is in a turn-on state during the charging and discharging operation.
The present invention provides an impedance comparison integrated circuit for detecting impedance variations with a high precision.
The present invention provides an impedance comparison integrated circuit having minimized power consumption.
In one aspect of the invention, there is provided an impedance comparison integrated circuit comprising: a current mirror means for providing current to a first input terminal and a second input terminal, respectively, during a first interval of every period; a discharging means for providing a discharging path to the first and the second input terminals, respectively, during a second interval of the every period; a differential amplification means for performing a differential amplification on signals input from the first and the second input terminals, respectively, during the first interval of the every period; and a first output means for outputting a first output signal to the first output terminal in response to the differential amplification means.
The current mirror means comprises: a first current source for generating an output current corresponding to a reference current provided by a bias resistor; a current sink section for providing a sink current corresponding to the output current of the first current source; and a second current source for providing currents to the first and the second input terminals, respectively, in response to the sink current.
The current mirror means further comprises a mode switching means, the mode switching means maintaining the current sink section a turn-on state in a high precision mode, turning on the current sink section during the first interval of the every period in the normal mode, and turning off the current sink section during the second interval of the every period in the normal mode.
The current mirror means minimizes a parasitic impedance difference of the integrating circuit for the first and second input terminals, and minimizes power consumption.
The first output means comprises: a first current sink means for providing a first sink current to a first node in response to the first differential amplified current signal; a second current sink means for providing a second sink current to a second node in response to the second differential amplified current signal; a current source coupled between the first node and a second node; and a capacitor coupled to the first node, for charging a current provided to the first node. Accordingly, the capacitor of the first output means prevents the chattering of the output signal.
The impedance comparison integrated circuit further comprises: a buffer means for buffering an output signal of the capacitor; a schmitt trigger means for performing a schmitt triggering operation on an output signal of the buffer means; and a second output means for outputting an output signal of the schmitt trigger means to a second output terminal.
The buffer means comprises: a first buffer coupled to the first node, for buffering the first output signal; and a second buffer coupled to the second node, for compensating a current loss of the first node due to the first buffer.
The first output means comprises: a first driving means for providing a sink current corresponding to the first differential amplified current signal to the first output terminal in a normal mode, the first driving means providing the sink current corresponding to the first differential amplified current signal to the first output terminal during the first interval of the every period in a high precision mode, and the first driving means providing a source current corresponding to the first differential amplified current signal to the first output terminal during the second interval in the high precision mode; and a second driving means for providing a source current corresponding to the second differential amplified current signal to the first output terminal in the normal mode, the second driving means providing the source current corresponding to the second differential amplified current signal to the first output terminal during the first interval of the every period in the high precision mode, and the second driving means providing a sink current corresponding to the second differential amplified current signal to the first output terminal during the second interval in the high precision mode.
The impedance comparison integrated circuit further comprises: a clock generating means for generating a clock signal having a predetermined period; a timing control means for receiving the clock signal and generating a timing control signal having a first interval and a second interval; a control input terminal for receiving an external control signal which selects the normal mode and the high precision mode; and a mode control signal generating means for generating a mode control signal base on the external control signal and the timing control signal so as to control the normal mode and the high precision mode. The normal mode begins when the control input terminal is connected to a pull up circuit and the control input terminal is left in a floating state. Also, the high precision mode begins when the control input terminal is connected to a pull down circuit and the control input terminal is left in a floating state.
The first input terminal and the second input terminal is disposed symmetrically with respect to a power terminal in a package so as to minimize a difference of parasitic impedance between the first input terminal and the second input terminal.
In another aspect, there is provided an impedance comparison integrated circuit package having an impedance comparison integrated circuit chip, wherein one chip or even number of chips is packaged in a body, first input pins and first output pins of at least one first chips is arranged in a first side of the package, second input pins and second output pins of at least one second chips corresponding to the first chips is arranged in a second side of the package.
The first and the second input pins are disposed symmetrically with respect to at least one pins in the first and second side of the package, or are disposed parallel.
In further aspect, there is provided a touch switch. The touch switch comprises: a case having a cubic shape, a horizontal supporting plate being disposed in the case, a lower space section formed on a lower surface of the horizontal supporting plate, and a upper space section formed on a upper surface of the horizontal supporting plate; a printed circuit board mounted on the horizontal supporting plate, the printed circuit board having a plurality of external lead lines projected toward the lower space section through the horizontal supporting plate, and an impedance comparison integrated circuit chip being mounted on the printed circuit board; a conductive elastic terminal installed on the printed circuit board, and projected toward the upper space section; and a insulating substrate installed on the case, the insulating substrate having a lower electrode layer and a upper electrode layer, the lower electrode layer being formed on a lower surface of the insulating substrate and being electrically connected to the conductive elastic terminal, and the upper electrode being formed on a upper surface of the insulating substrate and being externally touchable.
Preferably, a conductive elastic body is coupled to the upper electrode layer, a conductive pole is coupled to a center of the upper electrode layer, and the conductive pole is covered with a conductive rubber cap.
In further aspect, there is provided touch switch comprising: a case having a cubic shape, a horizontal supporting plate being disposed in the case, a lower space section formed on a lower surface of the horizontal supporting plate, and a upper space section formed on a upper surface of the horizontal supporting plate; a printed circuit board mounted on the case, the printed circuit board having a plurality of external lead lines projected toward the lower space section through the horizontal supporting plate, and an impedance comparison integrated circuit chip being mounted on a lower surface of the printed circuit board; and a electrode layer formed on the printed circuit board, and being electrically connected to the impedance comparison integrated circuit chip.
According to the impedance comparison integrated circuit of the present invention, a reference impedance device and a comparison impedance device are externally connected to the chip of the impedance comparison integrated circuit, currents are provided by means of current mirrors under same parasitic impedance conditions in the chip. Therefore, the input offset error of the differential amplification circuit is minimized to detect capacitance variation of about 0.01 pF.
Also, impedance variations are detected periodically, current consumption is minimized while sensing operation is not performed, so that a low current consumption, for example about 70 microamperes, can be accomplished.
The touch switch of the present invention minimize errors due to external parasitic impedance, provide impedance comparison with a high precision, can be easily installed, is strong against water and moisture and has a long life time due to a tightly sealed structure especially when used as a switch of home appliances